(1) Field of the Invention
The present invention relates to an image sensor comprising a sensor unit that is made up of a plurality of pixels and a plurality of scanning circuits, each of which has a dynamic logic circuit for outputting, with the use of different scanning methods, an output signal for selecting a row or a column in the sensor unit.
(2) Description of the Related Art
Recently, an image sensor using an amplifier-type MOS sensor has been developed. The image sensor is characterized by its high sensitivity and amplifies the signal detected by a photo diode for each cell indicating a pixel using a transistor.
A dynamic shift register is used as a circuit to scan horizontally or vertically a sensor unit which has pixels arranged two-dimensionally in such an image sensor as described above so as to enhance simplification, high integration and low power consumption of the circuit.
The conventional image sensor that is published in Japanese Laid-Open Application No. 2003-46879 has, as shown in FIG. 4, a sensor unit 10 and a plurality of scanning circuits 1, 2 so as to realize, for example, an electronic shutter function. The scanning circuits 1 and 2 are shift registers, each of which is composed of plural stages of unit registers, and output to the sensor unit 10 an output signal for reading out a pixel signal at a desired timing. The output is through a wire connected electrically.
The electronic shutter function of the image sensor is to adjust a charge storage time of the image sensor by means of its drive, and control electrically an exposure time instead of a physical function of an aperture. In more detail, the electronic shutter function can be achieved by resetting a signal charge accumulated in each of the pixels at a timing different from that of reading out the pixel signal. For example, the scanning circuit 1 outputs a row selection signal to be used for reading out a normal pixel signal while the scanning circuit 2 outputs a row selection signal to be used for resetting by the electronic shutter function.
In the diagram, the signals V1 and V2 are two-phase clock signals, on which the shifting operation is based. The clock signal V1 is inputted into the unit registers arranged in “2N+1”th (where N is an integer) stages while the clock signal V2 is inputted into the unit registers arranged in “2N”th stages. Thus, the unit registers in “2N+1”th stages and those in “2N+1”th stages operate in alternate shifts. The Transout 1 signal is outputted as a logical OR of two output signals outputted from the unit register at the first stage in the scanning circuits 1 and 2. The Transout 2 and 3 signals are outputted in the same manner as the Transout 1, but the unit registers to which they correspond are different.
FIG. 2A is a block diagram showing a structure of the unit register. As shown in the diagram, the unit register is composed of the NMOS-type transistors Tr4, Tr5 and the capacitor C1. The two-phase clock signals (the clock signals V1 or V2) on which the shifting operation is based are provided for the unit registers.
FIG. 2B shows an operation performed by the unit register in a case where the input signal In is at a high level. Since the input signal In is at a high level, a gate electrode of the transistor Tr4 is already at a high level due to a gate capacitor of the transistor Tr4 and a potential of the capacitor C1, before the rising edge of the clock signals V1/V2 ({circle around (1)} in the diagram). In this state, when the clock signals V1/V2 rise from a low level to a high level, a gate voltage In in the transistor Tr4 is boosted via the capacitor C1 ({circle around (2)} in the diagram). The potential under a gate becomes higher than a high level of the clock signals V1/V2 since a voltage higher than the high level of the clock signals V1/V2 is applied to the gate of the transistor Tr4, and thereby, the Out signal is outputted at the high level as that of the clock signals V1/V2 ({circle around (3)} in the diagram). When the clock signals V1/V2 fall to a low state, the Out signal is outputted at the low level as that of the clock signals V1/V2. In this case, the Next signal is outputted at a high level even after the fall of the clock signals V1/V2 since the high level is maintained in the gate capacitor of the transistor Tr5 that is unidirectional.
In a case where the input signal In is at a low level (or floating), the boost transistor Tr1 is not ON, therefore, both the Out signal and the Next signal are held at a low level (or floating) even though the clock signal Clk is inputted to them.
The reason why the respective outputs from the unit registers in the scanning circuits 1, 2 are connected via wires is that the output lines, other than the one outputting a selection signal at high level, are in a floating state, in the case where the scanning circuits 1, 2 are composed of shift registers operated using NMOS dynamic logic circuit. The logical OR of the outputs can be obtained via the wire connection.
Also, in reading out a flip horizontal or flip vertical image, the image sensor has a structure in which multiple scanning circuits with different scanning directions are arranged and an access signal for scanning vertically or horizontally is outputted to the sensor unit 10 by a wire connecting the outputs electrically. The scanning circuit 1 outputs the row selection signal used for reading out a normal pixel signal while the scanning circuit 2 outputs the row selection signal used for inversely reading out in order to scan in a reverse direction.
The image sensor having multiple shift registers, each of which has an NMOS dynamic logic circuit, however, has the following problem.
The problem, which the present invention attempts to overcome, is explained with reference to FIG. 3.
The V1, V2 are the two-phase clock signals while Transout1˜3 are signals respectively outputted to the sensor unit in correspondence with the first through third stages. The pulse P1 of the Transout 1 signal is generated when the clock signal V1 itself is outputted via the transistor Tr4. Similarly, the pulse P2 of the Transout 2 signal is generated when the clock signal V2 itself is outputted via the transistor Tr4 (in FIG. 2).
The Transout 3 signal and the Transout signals corresponding to the following stages are operated in the same manner.
Thus, a timing to output the pulse of a Transout signal is fixed according to the timing to output the pulse of the clock signal. It is therefore a problem that a Transout signal for electronic shutter use cannot be outputted at an arbitrary timing, for instance, the timings of P11, P22 and P33 shown in the diagram, within one horizontal period of time (1H in the diagram).